Design of Baugh-wooley Multiplier using Verilog HDL. Shruti D. Kale, Prof. Gauri N. Zade. India. Abstract: Multiplication represents one of the major holdups in. Adders and Multipliers. Baugh-Wooley Multiplier Design • To illustrate the mathematical transformation which is required, consider 4-bit signed operands X and. This project presents an efficient implementation of a high speed multiplier using the shift and adds method of. Baugh-Wooley Multiplier.

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The partial products have been generated using Peres gates. Conclusion is in section 6. This can be understood easily with the help of the comparison results shown in Table 1.

This gate is multiiplier known as Controlled-Not gate.

The proposed Baugh-Wooley multiplier design requires 20 gates. Showing of 11 references. The PFAG gate is used in the multi operand addition.

Received 18 April ; accepted 15 May ; published 15 June Topics Discussed in This Paper. The results and discussions of the proposed reversible Baugh-Wooley multiplier are presented in section 5. Let the numbers to be multiplied be A and B.

Computer arithmetic – algorithms and hardware designs Behrooz Parhami This reversible multiplier cell is useful in building up regularity in the array multipliers. Let X be one of the last two terms that can represent it with zero padding as.


A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog – Semantic Scholar

Function wise Peres Gate will be equal with the bit conversion generated by a Toffoli Gate succeeded by a Feynman Gate. These reversible multiplier cells are targeted for reversible Baugh-Wooley multiplier design. Complement reversible multiplier cell CMC.

This work also involves two steps as in [5].

Feynman Gate FG can be used as a copying gate. Skip to search form Skip to main content. Circuits and Systems07In this work we are proposing two reversible multiplier cells representing black and grey cells.

Besides, synthesizing reversible logic circuits is much difficult than conventional irreversible logic circuits due to the constraints.

Reversible multiplier cell MC. Synthesis of reversible multiplier cell. In this work also, like the previous works, the partial products have been generated using Peres gate. This gate is mainly used as a copying gate as fan-out is not allowed in reversible logic design.

Efficient realization of large size two’s complement multipliers using embedded blocks woolet FPGAs. References Publications referenced by this paper. The grey cells represent the multiplier cell.

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

In [6]the authors have proposed a new reversible gate called as HNG gate. BaughBruce A.


The additional input that is included to the irreversible function to convert baigh reversible is called constant input [4]. In our work, we have proposed a reversible multiplier cell which can be efficiently used in the Baugh Wooley multiplier.

The conclusion of the above discussion is that, it is evident that the proposed reversible Baugh-Wooley multiplier circuit design is better than the existing designs with respect to gate counts, garbage inputs and garbage outputs.

In the second step, the multi operand addition, Peres gates and Double Peres gates have been used.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog

In [8]the authors have proposed a new reversible gate muultiplier as RAM gate. The proposed reversible multiplier cells are capable of multiplying 2 bits in the current array and add the result with the sum and carry outputs of previous array.

It is comprehended that the number of gates, the constant inputs and garbage outputs values are fewer in number in the proposed design compared to the existing approaches.